It is often desirable in electronic applications to provide a fault indication when certain parameters are met. In high speed applications, high speed fault detection presents a problem since noise or other phenomenon may appear as an erroneous fault indication. Using filtering techniques to reduce the noise may introduce an error in the fault measurement by slowing down the ability to detect the fault. Because of this, it is undesirable to use filtering techniques to reduce unwanted noise.
One known solution to reduce erroneous fault indications is to provide a fault delay circuit at the output of the fault indication circuit. With such an arrangement, the output of the fault indication circuit is examined and unless the fault indication exists for a period of time longer than a predetermined period of time, the output of the fault delay circuit does not change from a no fault indication to an existing fault indication. In known integrated circuits to accomplish the latter, one pin of the integrated circuit is used to set the predetermined period of time for the delay in a particular application and a second pin is used to provide the fault indication signal. With the need to reduce package size and die area, yet provide more capability with an integrated circuit, it is desirable to reduce the pin count to accomplish fault indication.